1Field of the Invention
This invention is related to electronic circuits. In particular, this invention is related to electronic circuits capable of converting digital signals to analog signals.
2. Description of the Related Art
In modern day electronic systems, signals are often processed digitally while interfacing devices receive or transmit signals in an analog fashion. For example, in a video system of a computer, digital signals from the Central Processing Unit (CPU) are normally converted into analog signals before reaching the display monitor. In a robotics system, processed digital pulses are transformed into analog signals before feeding into a servo control mechanism. Digital-to-analog converters (DACs) are widely used for these purposes. As electronic circuits are built with faster and faster speed, DACs built with conventional design no longer can offer satisfactory performances. A few examples may serve as an illustration.
Reference is now made to FIG. 1 which shows a schematic diagram of a known DAC that employs an R-2R resistor network. The DAC, generally denoted by reference numeral 10, typically comprises an R-2R resistor network 12 connected to switches 14a to 14d. Resistor network 12 functions as a voltage divider for the reference supply voltages Vref1 and Vref2 applied at reference voltage terminals 16 and 18, respectively. The positions of the switches represent a digital input pattern which in turn proportionally divides the voltage difference between reference supply voltages Vref1 and Vref2. Each combination of switch positions corresponds to a specific stepped-voltage level Vout at the analog output terminal 20. Applying Kirchhoff's law to the DAC circuit 10, it can be shown that the relationship between the digital inputs, the positions of the switches 14a to 14d in this case, and the analog output at output terminal 20 can be expressed by the following equation: ##EQU1## where Vout is the stepped-analog output in volts;
Vref1 and Vref2 are reference supply voltages in volts; and PA0 D.sub.1, D.sub.2, D.sub.3 and D.sub.4 are digital input data with each assigned a numerical value of either 1 or 0.
In this example, DAC 10 is a four-bit circuit with the Most Significant Bit (MSB) being D.sub.4 and the Least Significant Bit (LSB) being D.sub.1. The four inputs yield sixteen digital input combinations (2.sup.4), with each combination corresponding to a stepped analog voltage level. For example, a binary number 0110 when applied to the switches 14a-14d would generate a stepped-analog output of [0.375.times.(Vref1-Vref2)] volts at output terminal 20.
The described circuit has a problem in the design of switches 14a-14 d. FIG. 2 shows switches 14a-14 d of FIG. 1 implemented with Complementary Metal Oxide Semiconductor (CMOS) switches 15a-15d. Each of CMOS switches 15a-15d includes the corresponding digital input terminals 54 to 60, p-channel MOS transistors 62a to 62d, and n-channel CMOS transistors 64a to 64d. For example, when a high voltage value close to Vref1 is applied to digital terminal 60 of CMOS switch 15a, transistor 64a is rendered active while transistor 62a is inactive with a high channel impedance. The switch's output circuit node 70a is therefore electrically tied to reference voltage supply terminal 18, which is sitting at a voltage level of Vref2. If a low voltage with a value close to Vref2 is applied to digital input terminal 60, the scenario is reversed. This time, p-channel transistor 62a is conductive and n-channel transistor 64a is turned off. Circuit node 70a is basically electrically tied to reference supply voltage terminal 16, which is at a voltage level of Vref1.
A problem arises during the transitional period when the voltage level at terminal 60 switches from Vref1 to Vref2, or vise versa. Depending upon the rise or fall time of the voltage signal at terminal 60, there is a short period when both transistors 62a and 64b are simultaneously turned on. The situation can be more easily understood with reference to FIG. 3, which shows the voltage and current waveforms at various terminals of DAC 30 superimposed on a common time axis. Waveform 72 represents the voltage level at terminal 60 as it ramps up from Vref2 to Vref1 within time period tr. Waveform 74 shows the voltage level at internal node 70a inside CMOS switch 15a. During an initial time period ending at time t1, p-channel transistor 62a is turned on and n-channel transistor 64a is turned off. However, at time t1, when the voltage at terminal 60 equals the threshold voltage Vthn of n-channel transistor 64a, a further rise in voltage at terminal 60 turns n-channel transistor 64a fully on. P-channel transistor 62a does not turn off until a later time t2, the time when voltage level at terminal 60 surpasses the negative threshold voltage Vthp of transistor 68a. Phrased differently, during the time period td between t1 and t2, transistors 62a and 64d are both turned on with low impedance conductive channels that draw a large amount of current between terminals 16 and 18. Reference voltage supplies (not shown) that would normally be used for Vref1 and Vref2 are typically designed with a predetermined current limit. The current drawn when transistors 62a and 64a are both on exceed this imposed current limit, resulting in an unpredictable output voltage form the reference voltage supply. To aggravate the matter further, a long period of time is required for the output voltage level to recover its original steady state value. As a consequence, the DAC output signal at terminal 20 may be distorted, and in some cases it can even be an erroneous output.
With ever increasing demands for faster electronics, the channel lengths of CMOS transistors are designed with shorter and shorter dimensions by integrated circuit manufacturers. The result is a much lower channel impedance. During the time td, higher and more unpredictable current is pumped out of the reference voltage supply. The sudden surge of current between reference voltage terminals 16 and 18 is illustrated as waveform 76 in FIG. 3.
To alleviate these problems, DACs have been designed in the past with extra circuitry for the prevention of excessive switching currents. A common solution is to insert a break-before-make circuit between the digital input terminal and the DAC switch. A schematic of such a circuit is shown in FIG. 4. The break-before-make circuits are designated by reference numerals 17a-17d. The logical symbols of the break-before-make circuit are represented in 17b-17c, while its circuit implementation is illustrated in 17d. With the break-before-make circuits 17a-17d in place, the p-channel transistors 62a to 62d and the n-channel transistors 64a to 64d are prevented from turning on simultaneously.
Each break-before-make circuit includes cross-coupled NAND gates, such as gates 82d and 84d in break-before-make circuit 17d, which constitute a bi-stable circuit capable of storing digital information. For ease of understanding, the circuits associated with the MSB will be discussed. In this instance, the break-before-make circuit 17a is connected to the MSB circuitry. Included in break-before-make circuit 17a are NAND gates 82a and 84a. Suppose NAND gate 82a initially stores a digital bit "1" and further suppose that the positive logic convention is adopted in this case. Node 90a at the output of gate 82a is then at a high voltage level corresponding to a logic "1", while node 92a at the output of gate 84a is at a low voltage level corresponding to a logic "0". Inside the DAC's MSB switching circuit 95a, transistor 62a is a n-channel transistor and is turned off, while transistor 64a is also a n-channel transistor but is turned on.
Suppose the voltage at digital input node 60 needs to be switched to a high voltage value for the purpose of toggling switching circuit 95a. A low-to-high signal is then applied at digital input terminal 60. The change of voltage is shown as waveform 94 in FIG. 5. After passing through a signal inverting circuit 86a, the waveform is converted to a high-to-low signal with a time lag of td1 due to the propagation delay passing through signal inverting circuit 86a. Waveform 96 represents the signal at node 61, which is located at the output of signal inverting circuit 86a as shown in FIG. 5. The signal at node 61 then travels to NAND gate 82a. Since the other input to NAND gate 82a is at a logic "0" level (coupled from the low output of NAND gate 84a), NAND gate 82a responds by switching its output from a low to a high level. The change of signal at output node 90a is shown as waveform 98 in FIG. 5. Notice that waveform 98 lags behind waveform 96 by a time lag td2 due to the propagational delay of the electrical signal passing through NAND gate 82a. Similarly, the electrical signal at node 90a is connected to an input to NAND gate 84a. The other input to NAND gate 84a is at a logic level "1" at this time because it is tied to digital input terminal 60, and assumes the same waveform 94. NAND gate 84a reacts by switching its output from a high level to a low level; the result is shown in FIG. 5 as waveform 100 with a time lag td3 with respect to waveform 98. Switching circuit 95a reacts by toggling transistor 62a on and transistor 62f off. During a blanking period tb both transistor are off. Blanking period tb is the time period in which break-before-make circuit 17a ensures that transistor 62a is fully turned off before transistor 62b is allowed to be turned on. There is never an overlap when both transistors are turned on, so that sudden surges in current demand and disruption in the operation of the reference voltage supply are avoided.
The addition of the break-before-make circuits significantly increases the complexity and cost of the DAC. More importantly, speed performance is also penalized. The summation of the time lags td1, td2 and td3 as shown in FIG. 5 adds an extra delay to the digital-to-analog conversion process. Consequently, circuits of this type have limited applications in high frequency operations.